SMIC N+3 node analysis shows density gains but lags Intel, TSMC
This digest was compiled by AI from multiple sources — links to the originals are below.
An analysis of Huawei's Kirin 9030 SoC reveals that SMIC's third-generation 7nm-class N+3 node achieves a transistor density of 113.4 million transistors per square millimeter, surpassing TSMC's N6. However, the chip's performance is comparable to flagship processors from three years ago, with a significant energy-efficiency disadvantage versus modern designs from Apple, Qualcomm, and others.
Density Achievement
SemiAnalysis' teardown of the Kirin 9030 indicates SMIC's N+3 node has a minimum metal pitch of 32.5nm, tighter than the ~36nm pitch used in Intel's Panther Lake CPU. The estimated transistor density of 113.4 MTr/mm² exceeds TSMC's N6 (107.7 MTr/mm²), which relies on multiple EUV layers. SMIC achieves this using DUV multi-patterning, including self-aligned quadruple patterning, and extensive design-technology co-optimization.
Performance Limitations
Despite density gains, the Kirin 9030 delivers performance comparable to flagship application processors from roughly three years ago. Huawei's highest-performing CPU core is characterized as roughly Cortex-X2-class in IPC, while Apple's much smaller efficiency cores reportedly outperform it in integer workloads and consume considerably less power. The chip has a substantial energy-efficiency disadvantage versus modern Apple, Qualcomm, MediaTek, and Samsung designs.
Comparison with Intel 18A
Although SMIC N+3 has a 32.5nm minimum metal pitch nominally tighter than the ~36nm pitch used in Panther Lake, Intel's 18A can support approximately 32nm metal pitches and offers higher transistor density and considerably better performance efficiency. SemiAnalysis notes that other key metrics like contacted gate pitch, standard cell height, and fin pitch are not disclosed, preventing a full comparison. The provocative comparison with Intel 18A is not justified given the Kirin 9030's lack of performance or efficiency leadership.
What's Next
Further teardowns of future SMIC chips may reveal additional node characteristics such as contacted gate pitch and fin pitch. It remains unclear whether SMIC can overcome yield and cost challenges to make N+3 commercially viable for high-performance applications.
1 source
SMIC N+3 node analysis shows density gains but lags Intel, TSMC
