Nvidia unveils NVHBM custom memory with 30% bandwidth gain
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Nvidia introduced NVHBM, a custom high-bandwidth memory architecture, on August 26. The company claims it delivers up to 30% more memory bandwidth per stack and 15% lower power consumption compared with standard HBM4E samples. Amazon's Annapurna Labs is the first named partner for the technology, which is expected to ship in volume in 2027.
Key Facts
- Nvidia claims NVHBM delivers up to 30% more memory bandwidth per stack, 15% lower HBM power consumption, and up to 25% more usable area on the accelerator die compared with standard HBM4E samples.
- Amazon's Annapurna Labs is the first named partner for NVHBM and will support NVLink Fusion with Trainium4.
- NVHBM is expected to ship in volume in 2027, while HBM4E samples were shipped by Samsung in late May 2026 and SK hynix around June 2026.
- Marvell announced a similar custom HBM approach in December 2024 with Micron, Samsung, and SK hynix, claiming up to 25% more compute area and a 70% reduction in memory interface power.
NVHBM Architecture
NVHBM moves Nvidia's memory controller into the base die of the 3D stack, replacing the standard JEDEC parallel bus with a narrower, serialized die-to-die link. Nvidia's technical blog reports up to 67% reduction in interface and support area against the JEDEC HBM4E standard. The architecture is designed to address bandwidth limitations for frontier-level AI models.
Partner and Market Timing
Amazon's Annapurna Labs is the first named participant in the NVLink Fusion program and will support it with Trainium4, though Nvidia's blog does not explicitly mention NVHBM for that chip. NVHBM is gated behind NVLink Fusion, Nvidia's program for connecting third-party accelerators to its rack-scale platform. Counterpoint Research analyst Neil Shah said the technology is not new, but the distribution is.
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