AI system designs AI accelerator chip from spec to FPGA prototype in under two weeks

September 21, 2026 at 12:25 AM2 min

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Architect Labs Platform autonomously designed the Redwood AI accelerator from a text specification to a working FPGA implementation in under two weeks. The system handled performance modeling, circuit generation, verification, firmware, and software kernels without engineer intervention. A revised version appeared on FPGA within 48 hours of a specification change.

Key Facts

Architect Labs Platform completed the full design cycle for the Redwood AI accelerator in under two weeks.
A revised version appeared on FPGA within 48 hours of a specification change.
Redwood Nano on FPGA achieved 12.1 tokens/s at 250 MHz on Qwen3 0.6B, versus 28 tokens/s at 1020 MHz for Nvidia Jetson Orin Nano.
For a future Samsung 8nm-class version, researchers project 49 tokens/s at 1.335 W versus 2.59 W for Jetson Orin Nano.
All blocks reached 95% code and functional coverage, and the first RTL version sent from simulation to FPGA showed no errors.

Autonomous Design Process

Engineers provided only a high-level text specification, after which Architect Labs Platform independently performed performance modeling, generated the digital circuit description, conducted testing and verification, and prepared firmware and software kernels. The full cycle took under two weeks, and a new version appeared on FPGA within 48 hours of a specification change. Architect Labs replaces the traditional stage-by-stage design flow with a unified optimization loop in which hardware and software are designed and tested jointly. The system can explore a microarchitecture design space an order of magnitude wider than a human team in the same timeframe, according to the developers. For individual blocks, it generated multiple variants with different control logic and data paths, then compared them by area and timing characteristics.

Performance and Architecture

Redwood exists only as an FPGA implementation, so claims of superiority over any company refer to calculations rather than a physical chip. In the experiment, Redwood Nano on FPGA achieved 12.1 tokens/s at 250 MHz on Qwen3 0.6B, while Nvidia Jetson Orin Nano reached 28 tokens/s at 1020 MHz. For a future Samsung 8nm-class version, researchers project 49 tokens/s at 1.335 W versus 2.59 W for Jetson Orin Nano, a calculated 1.75x performance advantage and 3.4x performance-per-watt advantage. The Redwood architecture reduces latency and energy use by placing data near compute units, using identical tile-based blocks that pass data to neighbors instead of constantly accessing shared memory. Control is separated from computation, individual blocks can slow down or power off, and a built-in global timer schedules kernel execution.

Verification and Self-Improvement

All blocks reached 95% code coverage and functional coverage, and the first RTL version sent from simulation to FPGA showed no errors. Researchers separately conducted an experiment they describe as an early form of recursive self-improvement.